Based Low Footprint Security Chip for Portable

Elliptic Curve Cryptography is one of the most preferred public key Cryptography algorithms known for its security strength and reduced key size. This makes ECC most suitable for implementing the hardware security chip for providing security services in portable embedded devices. This paper presents an area efficient Security Chip housing ECC algorithm for data encryption over binary field and hybrid multiplier for performing cryptographic multiplications. In proposed FPGA security chip, revised and simplified double point multiplication algorithm is adopted and to achieve further reduction, new low footprint hybrid multiplier is integrated. This hybrid multiplier integrates traditional Karatsuba Multiplier with systolic multiplier. The proposed hybrid multiplier does the initial recursion using the systolic algorithm while final small sized multiplications are accomplished using the Karatsuba algorithm The complete Security Chip housing ECC encryption engine and multiplier module is synthesized and simulated using Xilinx 14.4 software and is implemented on Xilinx Virtex-4 xc4vlx200ff1513 FPGA. Experimental results show proposed Security Chip utilizes very little FPGA resources, when comparing with other such architectures.